1. Technical Field
The present invention relates to analog-to-digital converters in general, and in particular to a continuous-time delta-sigma analog-to-digital converter featuring clock-jitter error shaping in a feedback digital-to-analog converter.
2. Description of Related Art
Continuous-time delta-sigma analog-to-digital converters (ADCs) have gained significant attention in the field of wideband receivers because of their ability to operate at high speeds with lower power consumptions when compared to their discrete-time counterparts. However, continuous-time delta-sigma ADCs suffer from critical limitations due to their high sensitivity to pulse-width jitter in feedback digital-to-analog converter (DAC) waveforms.
The above mentioned pulse-width jitter problem arises from the random variations of DAC sampling clock edges that cause uncertainty in the integrated values at the outputs of loop filter integrators. This problem is equivalent to the application of a random phase modulation to the digital signal coming in a feedback path, which causes a part of the shaped noise, outside the signal band, to fall into the band of interest. The pulse-width jitter in the DAC feeding the first stage of the loop filter of a continuous-time delta-sigma ADC is very harmful because its resulting error appears directly at the output of the ADC without any shaping or suppression.
Consequently, it would be desirable to provide an improved continuous-time delta-sigma ADC capable of handling pulse-width jitter problems.